The invention relates to devices and methods for packaging integrated circuit (IC) devices. More particularly, the invention relates to devices and methods using vias among adjoining layers of semiconductor packages for improved bonding and reduced mechanical stress.
In use, integrated circuits (ICs) generally require electrical connections to a substrate to form a package providing electrical connections to additional electronic devices. In general a package substrate may include, but not be limited to, multiple layers of semiconductor, mask, conductive and non-conductive materials, dielectrics, encapsulates, thermal management items, etc., depending upon the complexity of the electrical connections to be made. In practice, the more layers, the higher the manufacturing effort and expense. Frequently an IC die is included on a package substrate along with other ICs or one or more discrete passive components such as resistors, capacitors, and so forth.
A die is typically attached to a xe2x80x9cbond padxe2x80x9d using an adhesive such as epoxy, solder, or some form of eutectic metal that attaches the die without introducing damaging temperature, stress, or contamination into the semiconductor die. This xe2x80x9cdie attach materialxe2x80x9d can be purely mechanical or chemical bonding or a combination of chemical/mechanical bonds to form electrical and/or thermal paths, or neither, serving only as a substrate. With any combination thereof, the ability of the attach material to maintain a bond is critical in most applications. Failure of the die attach bond, or other bonded interface, can result in package failure resulting in overall electrical failure in the final system.
A common method to xe2x80x9cbondxe2x80x9d a semiconductor to a PC board is with a xe2x80x9cleadedxe2x80x9d package. The package leads are typically bonded with a combination of metals that reflow (melt) typically around 160 to 260 degrees Celsius, achieving a mechanical, chemical or chemical/mechanical bond between the lead and the PC board. Epoxy pastes are also used to form bonds. Such bonds may serve as the electrical contact between the device and the board and may also serve as a thermal path or as neither, merely affixing the components together.
Failure in the die attach, or various layers, usually shows as a xe2x80x9cdelamination,xe2x80x9d or separation, at one or more of the interfaces. This failure may occur in the bulk of the die attach material, at the die attach to die, or die attach to bond pad interface or one of the many other layers. This separation is visually observed as a xe2x80x9ccrackxe2x80x9d in the one or more of the layers. Likewise, failure at the lead to bond pad may show similar failure mechanisms.
Packaging methods and devices providing for strong and durable bonds resistant to mechanical failure/fatigue would be useful and desirable in the arts. Increases in bonding strength for packaged devices would also lead to flexibility in terms of improvements in package size and concurrent design limitations.
In general, devices and methods providing improved semiconductor package performance resistant to mechanical stresses are disclosed.
According to one aspect of the invention, a multi-layer laminated semiconductor package includes first and second layers, at least one of which is perforated by vias. The layers adjoin one another along approximately planar surfaces with the vias providing additional bonding structure. An attach material is provided between the attaching surfaces of the layers and within the vias, ensuring a secure bond.
According to another aspect of the invention, one of the layers is a semiconductor die.
According to another aspect of the invention, one of the layers is a semiconductor die lead foot.
According to other aspects of the invention, one of the layers is a bond pad, substrate or tape. Various bond surfaces may be used depending on package type.
According to still another aspect of the invention, the vias include an expanded end portion at a layer surface opposing the attach surface for accepting attach material.
According to an additional aspect of the invention, the vias are arranged at predetermined intervals.
According to yet another aspect of the invention, the vias are arranged at predetermined predicted stress points.
According to another aspect of the invention, a method is provided for bonding the layers of a multi-layer laminated semiconductor package. Steps in the method include perforating one or more layers with one or more vias. In a further step, attach material is introduced into the vias and between the layers such that the layers are securely bonded.
According to still another aspect of the invention, the perforating vias are formed by drilling.
According to yet another aspect of the invention, a step of predicting potential stress points is used for determining the arrangement of vias.
Technical advantages provided by the invention include, but are not limited to, stronger and improved failure-resistant bonds resulting in increased reliability, performance, and a potential reduction in the amount of attach material necessary for bonding. Further advantages are realized in the potential for making smaller packages due to flexibility for changes in lead and package geometry. For example, potential limiting factors in lead design, such as the minimum requirements for adequate solder coverage become less limiting with the use of the invention. Improvements in the reflow profiles in solder bonds may also be achieved.